Wires on a chip are interesting. On a PCB you mostly have just two cases to deal with: low edge rate case, the trace is equivalent to a capacitor. Fast edge rate case, the trace is equivalent to a transmission line with a characteristic impedance, such as a coax cable- signals will bounce and you have to worry about termination. In both of these cases you can pretty much assume that resistance is zero (except for very high edge rates).
Now on a chip the traces are so thin that resistance is significant and can not be ignored. The trace can be modeled as a distributed or lumped RC circuit. A consequence is that the delay is a quadratic function of its length (doubling the length of the wire quadruples its delay). It becomes worthwhile to add repeaters. I wonder if these show up in 8086..
On the other hand, "For on-chip wires with a maximum length of 1 cm, one should only worry about transmission line effects when tr < 150 psec"
Well yes and no - at the time the 8086 was designed gate capacitance dominated over wire RC delays - early design tools (sort of pre-late 90s, way after the original 8086) didn't bother with calculating RC delays during synthesis and we only really dealt with them in late static timing analysis (and really then only for a few long lines).
Essentially as chip features got smaller wire resistance didn't scale the same as gate capacitance (partly it's edge effects) and our tools needed to change as RC delays started to dominate
Now on a chip the traces are so thin that resistance is significant and can not be ignored. The trace can be modeled as a distributed or lumped RC circuit. A consequence is that the delay is a quadratic function of its length (doubling the length of the wire quadruples its delay). It becomes worthwhile to add repeaters. I wonder if these show up in 8086..
On the other hand, "For on-chip wires with a maximum length of 1 cm, one should only worry about transmission line effects when tr < 150 psec"
http://bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_f01/No...